1. Field of the Invention
The present invention relates to an analysis and design apparatus for semiconductor device and an analysis and design method for semiconductor device. In particular, the present invention relates to an analysis and design apparatus for semiconductor device and an analysis and design method for semiconductor device, which utilize a transistor model using accurate channel impurity concentration distribution.
2. Description of Related Art
A technique for analyzing characteristics of electronic element such as a transistor has been known. For example, “Analytical Subthreshold Surface Potential Model for Pocket n-MOSFETs”, Y. S. Pang, et al., IEEE Trans. On Electron Devices, Vol. 49, No. 12, pp. 2209-2216, (2002) discloses a technique for analyzing characteristics of a MOS transistor. Hereinafter, this paper is also referred to as “Pang” in this specification. FIG. 1 is a sectional view showing a structure of a MOS transistor of this model. A MOS transistor 150 as the model transistor includes a source region 155, a drain region 153, a gate oxide film 152, a channel region 154 and a gate electrode 151. The source region 155 and the drain region 153 are provided on a surface region of a semiconductor substrate across the channel region 154. The gate oxide film 152 and the gate oxide film 152 are laminated in this order so as to cover the channel region 154. According to this technique, the channel region 154 is divided into three regions depending on a channel impurity concentration as an impurity concentration in the channel region 154 in a depth direction. The widths of the regions are defined as Lp, Lc, Lp, respectively, and the impurity concentrations of the regions are defined as Np, Nc, Np, respectively. Here, Lp, Lc, Np, Nc are set as model parameters so as to correspond to actual transistor channel impurity concentration distribution well. Next, a surface potential in each region of the channel region 154 is obtained by solving a Poisson equation using the surface potential as a variable. Subsequently, electric characteristics of the transistor are calculated using the obtained surface potential. Here, the electric characteristics of the transistor are exemplified by a gate capacitance Cgg—gate voltage Vg characteristic and a threshold voltage Vth—substrate voltage Vb characteristic (or a drain current Id—substrate voltage Vb characteristic). A method described in Pang and well-known conventional method can be adopted as a method of calculating these electric characteristics. Here, in the case where the obtained transistor electric characteristics (calculated values) do not correspond to actual transistor electric characteristics (measured values), the model parameters are adjusted and the above-mentioned calculation is repeated. When the calculated values correspond to the measured values, it is deemed that the model parameter reproduce the actual transistor channel impurity concentration distribution. Then, analysis of a semiconductor element and design of a semiconductor circuit are performed using the obtained model parameters.
Another method of calculating the electric characteristics of the transistor is described in the paper of “Unified complete MOSFET model for analysis of digital and analog circuits”, M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, and D. Savignac, Proc. IEEE Trans. On Comput.-AidedDes./Int. Conf. Comput. Aided Des., vol. 15, no. 1, pp. 1-7, January (1996). Hereinafter, this paper is also referred to as “Miura” in this specification.
We have now discovered the following facts. According to the above-mentioned technique in Pang, the effect that effective channel impurity concentration in the vicinity of the source region 155 and the drain region 153 decreases due to influence of the source region 155 and the drain region 153 is not incorporated. For this reason, it is deemed that the surface potential calculated using the above-mentioned model parameters cannot represent the actual surface potential accurately. Therefore, even if the transistor electric characteristics are obtained using the calculated surface potential, the actual transistor electric characteristics cannot be represented with high accuracy. In other words, the transistor electric characteristics of the transistor model in Pang cannot represent the actual transistor electric characteristics with high accuracy. As a result, non-negligible errors may be observed in analysis of the semiconductor element and design of the semiconductor circuit.